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| C8051F230 25 MIPS, 8 kB Flash, 48-Pin Mixed-Signal MCU Analog Peripherals Two comparators High-Speed 8051 C Core - - Programmable hysteresis Configurable to generate interrupts or reset VDD Monitor and Brown-out Detector Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 25 MIPS throughput with 25 MHz system clock Expanded interrupt handler; up to 21 interrupt sources 256 bytes data RAM 8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are reserved) 32 port I/O; all are 5 V tolerant Hardware SPITM and UART serial ports available concurrently 3 general-purpose 16-bit counter/timers Dedicated watchdog timer; bidirectional reset Internal programmable oscillator: 2-16 MHz External oscillator: Crystal, RC, C, or Clock Can switch between clock sources on-the-fly On-Chip JTAG Debug Memory On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit emulation Supports breakpoints, single stepping, watchpoints, inspect/modify memory, and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets Fully compliant with IEEE 1149.1 specification Typical operating current: 9 mA at 25 MHz Typical stop mode current: <0.1 uA Digital Peripherals Supply Voltage: 2.7 to 3.6 V Clock Sources 48-Pin TQFP - Temperature Range: -40 to +85 C VDD VDD GND GND NC NC NC NC Analog/Digital Power Port 0 Latch UART Timer 0 Timer 1 Timer 2 P 0 M U X P 0 D r v P0.0/TX P0.1/RX P0.2//INT0 P0.3//INT1 P0.4/T0 P0.5/T1 P0.6/T2 P0.7/T2EX TCK TMS TDI TDO RST JTAG Logic Debug HW Reset 8 0 5 1 C o r e 8 kB FLASH 256 byte RAM Port 1 Latch CP0 CP0+ CP0 P 1 M U X P 1 D r v CP0CP1+ CP1 CP1 P1.0/CP0+ P1.1/CP0P1.2/CP0 P1.3/CP1+ P1.4/CP1P1.5/CP1 P1.6/SYSCLK P1.7 MONEN VDD Monitor External Oscillator Circuit Internal Oscillator CP1SYSCLK WDT Port 2 Latch SPI XTAL1 XTAL2 SFR Bus P 2 M U X P 2 D r v P 3 System Clock P2.0/SCK P2.1/MISO P2.2/MOSI P2.3/NSS P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Port 3 Latch D r v General Purpose Copyright (c) 2004 by Silicon Laboratories 6.15.2004 C8051F230 25 MIPS, 8 kB Flash, 48-Pin Mixed-Signal MCU Selected Electrical Specifications (TA = -40 to +85 C, VDD = 2.7 V unless otherwise specified unless otherwise specified) PARAMETER CONDITIONS GLOBAL CHARACTERISTICS Supply Voltage Supply Current (CPU Clock = 25 MHz active) Clock = 1 MHz Clock = 32 kHz; VDD Monitor Disabled Supply Current Oscillator not running; VDD Monitor (shutdown) Enabled Oscillator not running; VDD Monitor Disabled Clock Frequency Range COMPARATORS Supply Current (each comparator) Response Time (CP+) - (CP-) = 100 mV MIN 2.7 9 0.4 11 10 0.1 DC 1.5 4.0 25 TYP MAX 3.6 UNITS V mA mA A A A MHz A s Package Information D D1 C8051F226DK Development Kit MIN NOM MAX (mm) (mm) (mm) 1.20 0.15 A E1 E A1 0.05 A2 0.95 1.00 1.05 b 48 PIN 1 IDENTIFIER A2 0.17 0.22 0.27 9.00 7.00 0.50 9.00 7.00 - D D1 1 e e E A b A1 E1 General Purpose Copyright (c) 2004 by Silicon Laboratories 6.15.2004 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders |
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